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SOLOMON SYSTECH
SEMICONDUCTOR TECHNICAL DATA
SSD1815B
Advance Information LCD Segment / Common Driver with Controller
CMOS
SSD1815B is a single-chip CMOS LCD drivers with controllers for dot-matrix graphic liquid crystal display system. SSD1815B is capable to drive 132 Segments, 64 Commons and 1 icon line by its 197 high voltage driving output. SSD1815B display data directly from their internal 132 x 65 bits Graphic Display Data RAM (GDDRAM). Data/Commands are sent from common MCU through 8-bit Parallel or Serial Interface. The selection of whether 6800- or 8080-series compatible Parallel Interface or Serial Peripheral Interface is done by hardware pins configuration. SSD1815B embeds a DC-DC Converter, an On-Chip Bias Divider and an On-Chip Oscillator which reduce the number of external components. With the advanced design on minimizing power consumption and die/package layout, SSD1815B is suitable for any portable battery-driven applications requiring a long operation period with a compact size.
This document contains information on a new product. Specifications and information herein and subject to change without notice.
Copyright (c) 2001 SOLOMON Systech Limited
Rev 1.6 07/2002
FEATURES
Dot-matrix Display with separated Icon Line, 132 x 64 + 1 Icon Line Single Supply Operation, 2.4V ~ 3.5V Minimum -12.0V LCD Driving Output Voltage Low Current Sleep Mode On-Chip Voltage Generator or External LCD Driving Power Supply Selectable 2X / 3X / 4X On-Chip DC-DC Converter On-Chip Oscillator Programmable Multiplex ratio in dot-matrix display area, 1Mux ~ 64Mux On-Chip Bias Divider Programmable bias ratio, 1/4, 1/5, 1/6, 1/7, 1/8, 1/9 8-bit 6800-series Parallel Interface, 8-bit 8080-series Parallel Interface and Serial Peripheral Interface On-Chip 132 X 65 Graphic Display Data RAM Re-mapping of Row and Column Drivers Vertical Scrolling Display Offset Control 64 Level Internal Contrast Control External Contrast Control Programmable LCD Driving Voltage Temperature Coefficients Available in Gold Bump Die and TAB (Tape Automated Bonding) Package
ORDERING INFORMATION
Table 1 SSD1815B Ordering Information
Ordering Part Number SSD1815BZ SSD1815BT SSD1815BT2 Seg Com Default Bias Package Form Gold Bump Die 70mm Folding TAB 48mm Folding TAB Reference Figure 2 on page 5 Figure 16 on page 32 Figure 18 on page 34
132
64 + 1
1/9, 1/7
SOLOMON
Rev1.6 07/2002
SSD1815B 3
BLOCK DIAGRAM
ROW0 ~ ROW63
ICONS
SEG0~SEG131
HV Buffer Cell Level Shifter
Level Selector V L6 V L5 V L4 V L3 V L2 V DD VF LCD Driving Voltage Generator 2X / 3X / 4X DC/DC Converter, Voltage Regulator, Bias Divider, Contrast Control, Temperature Compensation V EE V SS1 C3N C 1P C 1N C 2N C 2P V FS HPM IRS
Display Data Latch MSTAT M Display Timing Generator
DOF M/S
CL CLS
Oscillator
GDDRAM 132 X 65 Bits
Command Decoder
V SS VDD Command Interface Parallel / Serial Interface
RES P/S CS1 CS2 D/C
E R/W C68/80 (RD) (WR)
D7 D6 D 5 D 4 D 3 D 2 D 1 D0 (SDA) (SCK)
Figure 1 SSD1815B Block Diagram
SSD1815B 4
Rev 1.6 07/2002
SOLOMON
PIN ARRANGEMENT
IC ON S R OW0 R OW1 R OW2 R OW3 R OW4 R OW5 R OW6 R OW7 R OW8 R OW9 R OW10 R OW11 R OW12 R OW13 R OW14 R OW15 R OW16 R OW17 R OW18 R OW19 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20
137 Cen ter : 3816.05, -305.2 Size: 100.1u x 10 0.1 u Center: 381 9.2 , -419.2 Size: 99 .75u x 99.7 5u
115
: :
SEG110 SEG111 SEG112 SEG113 SEG114 SEG115 SEG116 SEG117 SEG118 SEG119 SEG120 SEG121 SEG122 SEG123 SEG124 SEG125 SEG126 SEG127 SEG128 SEG129 SEG130 SEG131
: :
268
1
ROW20 ROW21 : : ROW30 ROW31 VDD IRS VSS /HPM VDD P/S C68/80 VSS CLS M/S VDD NC NC VDD VDD VF VF VL6 VL6 VL6 VL5 VL5 VL4 VL4 VL4 VL3 VL3 VL3 VL2 VL2 VDD VDD VFS VFS VSS VSS C2P C2P C2P C2N C2N C2N C2N C1N C1N C1N C1P C1P C1P C3N C3N C3N C3N VEE VEE VEE VEE VSS1 VSS1 VSS1 VSS1 VSS VSS VSS VDD VDD VDD VDD D7 (SDA) D6 (SCK) D5 D4 D3 D2 D1 D0 VDD E(/RD) R/W(/WR) VSS D/C /RES VDD CS2 /CS1 VSS /DOF CL M MSTAT NC ICONS ROW63 ROW62 ROW61 : : ROW54 ROW53
Center: 370 1.0 75, -30 4.5 Ra dius: 50.925u
Gold Bump Alignment Mark This alignment mark contains gold bump for IC bumping process alignment and IC identifications. No conductive tracks should be laid underneath this mark to avoid short circuit.
Note: 1. This diagram showing Die Face Up view. 2. Coordinates and Size of all alignment marks are in unit um and w.r.t. center of the chip.
Y
Center: -38 80.6 25, 20 5.6 25 Size: 99 .75 u x 99.75u
(0,0)
Center: 389 .72 5, -201 .6 Radius: 27.125 u
x
Die Size: Die Thickness: Bump Pitch: Bump Height:
10.977mm X 1.912mm 550 +/-25um 76.2 um [Min] Nominal 18um Tolerance <4um within die <8um within lot
PIN #1
Figure 2 SSD1815B Gold Bump Die Pin Assignment
SOLOMON
R OW32 R OW33 R OW34 R OW35 R OW36 R OW37 R OW38 R OW39 R OW40 R OW41 R OW42 R OW43 R OW44 R OW45 R OW46 R OW47 R OW48 R OW49 R OW50 R OW51 R OW52
Rev1.6 07/2002
SSD1815B 5
Table 2 SSD1815B Gold Bump Die Pad Coordinates
PAD # NAME 1 ROW53 2 ROW54 3 ROW55 4 ROW56 5 ROW57 6 ROW58 7 ROW59 8 ROW60 9 ROW61 10 ROW62 11 ROW63 12 ICONS 13 NC 14 MSTAT 15 M 16 CL 17 /DOF 18 VSS 19 /CS1 20 CS2 21 VDD 22 /RES 23 D/C 24 VSS 25 R/W 26 E/RD 27 VDD 28 D0 29 D1 30 D2 31 D3 32 D4 33 D5 34 D6 35 D7 36 VDD 37 VDD 38 VDD 39 VDD 40 VSS 41 VSS 42 VSS 43 VSS1 44 VSS1 45 VSS1 46 VSS1 47 VEE 48 VEE 49 VEE 50 VEE 51 C3N 52 C3N 53 C3N 54 C3N 55 C1P 56 C1P 57 C1P 58 C1N 59 C1N 60 C1N Die Size: 10.977mm Bump Size: Pad # X [um] 1 - 12 43.5 13 - 103 61.7 104 - 115 43.5 X -4958.45 -4882.15 -4805.85 -4729.55 -4653.25 -4576.95 -4500.65 -4424.35 -4348.05 -4271.75 -4195.45 -4119.15 -4000.50 -3911.60 -3822.70 -3733.80 -3644.90 -3556.00 -3467.10 -3378.20 -3289.30 -3200.40 -3111.50 -3022.60 -2933.70 -2844.80 -2755.90 -2667.00 -2578.10 -2489.20 -2400.30 -2311.40 -2222.50 -2133.60 -2044.70 -1955.80 -1866.90 -1778.00 -1689.10 -1600.20 -1511.30 -1422.40 -1333.50 -1244.60 -1155.70 -1066.80 -977.90 -889.00 -800.10 -711.20 -622.30 -533.40 -444.50 -355.60 -266.70 -177.80 -88.90 0.00 88.90 177.80 X Y [um] 101.6 61.7 101.6 Y -751.98 -751.98 -751.98 -751.98 -751.98 -751.98 -751.98 -751.98 -751.98 -751.98 -751.98 -751.98 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 1.912mm Pad # 116 - 136 PAD # 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 NAME C2N C2N C2N C2N C2P C2P C2P VSS VSS VFS VFS VDD VDD VL2 VL2 VL3 VL3 VL3 VL4 VL4 VL4 VL5 VL5 VL6 VL6 VL6 VF VF VDD VDD NC NC VDD M/S CLS VSS C68/80 P/S VDD /HPM VSS IRS VDD ROW31 ROW30 ROW29 ROW28 ROW27 ROW26 ROW25 ROW24 ROW23 ROW22 ROW21 ROW20 X 266.70 355.60 444.50 533.40 622.30 711.20 800.10 889.00 977.90 1066.80 1155.70 1244.60 1333.50 1422.40 1511.30 1600.20 1689.10 1778.00 1866.90 1955.80 2044.70 2133.60 2222.50 2311.40 2400.30 2489.20 2578.10 2667.00 2755.90 2844.80 2933.70 3022.60 3111.50 3200.40 3289.30 3378.20 3467.10 3556.00 3644.90 3733.80 3822.70 3911.60 4000.50 4119.15 4195.45 4271.75 4348.05 4424.35 4500.65 4576.95 4653.25 4729.55 4805.85 4882.15 4958.45 Y -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -751.98 -751.98 -751.98 -751.98 -751.98 -751.98 -751.98 -751.98 -751.98 -751.98 -751.98 -751.98 PAD # 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 NAME ROW19 ROW18 ROW17 ROW16 ROW15 ROW14 ROW13 ROW12 ROW11 ROW10 ROW9 ROW8 ROW7 ROW6 ROW5 ROW4 ROW3 ROW2 ROW1 ROW0 ICONS X 5285.18 5285.18 5285.18 5285.18 5285.18 5285.18 5285.18 5285.18 5285.18 5285.18 5285.18 5285.18 5285.18 5285.18 5285.18 5285.18 5285.18 5285.18 5285.18 5285.18 5285.18 Y -768.78 -692.48 -616.18 -539.88 -463.58 -387.28 -310.98 -234.68 -158.38 -82.08 -5.78 70.53 146.83 223.13 299.43 375.73 452.03 528.33 604.63 680.93 757.23
Y
PIN268 (0,0) PIN 1
PIN137 x PIN115
Die Size: 10.977mm X 1.912mm Bump Height: - nominal: 18um - tolerance:<4um (within die) <6um (within wafer) <8um (within lot) Unit in um unless otherwise specified.
X [um] 101.6
Y [um] 43.5
Pad # 137 - 268
X [um] 43.5
Y [um] 101.6
Pad # 269 - 289
X [um] 101.6
Y [um] 43.5
Gold bump width tolerance: +/- 3um.
SSD1815B 6
Rev 1.6 07/2002
SOLOMON
PAD # 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202
NAME SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 SEG64 SEG65
X 4997.65 4921.35 4845.05 4768.75 4692.45 4616.15 4539.85 4463.55 4387.25 4310.95 4234.65 4158.35 4082.05 4005.75 3929.45 3853.15 3776.85 3700.55 3624.25 3547.95 3471.65 3395.35 3319.05 3242.75 3166.45 3090.15 3013.85 2937.55 2861.25 2784.95 2708.65 2632.35 2556.05 2479.75 2403.45 2327.15 2250.85 2174.55 2098.25 2021.95 1945.65 1869.35 1793.05 1716.75 1640.45 1564.15 1487.85 1411.55 1335.25 1258.95 1182.65 1106.35 1030.05 953.75 877.45 801.15 724.85 648.55 572.25 495.95 419.65 343.35 267.05 190.75 114.45 38.15
Y 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98
PAD # 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268
NAME SEG66 SEG67 SEG68 SEG69 SEG70 SEG71 SEG72 SEG73 SEG74 SEG75 SEG76 SEG77 SEG78 SEG79 SEG80 SEG81 SEG82 SEG83 SEG84 SEG85 SEG86 SEG87 SEG88 SEG89 SEG90 SEG91 SEG92 SEG93 SEG94 SEG95 SEG96 SEG97 SEG98 SEG99 SEG100 SEG101 SEG102 SEG103 SEG104 SEG105 SEG106 SEG107 SEG108 SEG109 SEG110 SEG111 SEG112 SEG113 SEG114 SEG115 SEG116 SEG117 SEG118 SEG119 SEG120 SEG121 SEG122 SEG123 SEG124 SEG125 SEG126 SEG127 SEG128 SEG129 SEG130 SEG131
X -38.15 -114.45 -190.75 -267.05 -343.35 -419.65 -495.95 -572.25 -648.55 -724.85 -801.15 -877.45 -953.75 -1030.05 -1106.35 -1182.65 -1258.95 -1335.25 -1411.55 -1487.85 -1564.15 -1640.45 -1716.75 -1793.05 -1869.35 -1945.65 -2021.95 -2098.25 -2174.55 -2250.85 -2327.15 -2403.45 -2479.75 -2556.05 -2632.35 -2708.65 -2784.95 -2861.25 -2937.55 -3013.85 -3090.15 -3166.45 -3242.75 -3319.05 -3395.35 -3471.65 -3547.95 -3624.25 -3700.55 -3776.85 -3853.15 -3929.45 -4005.75 -4082.05 -4158.35 -4234.65 -4310.95 -4387.25 -4463.55 -4539.85 -4616.15 -4692.45 -4768.75 -4845.05 -4921.35 -4997.65
Y 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98
PAD # 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289
NAME ROW32 ROW33 ROW34 ROW35 ROW36 ROW37 ROW38 ROW39 ROW40 ROW41 ROW42 ROW43 ROW44 ROW45 ROW46 ROW47 ROW48 ROW49 ROW50 ROW51 ROW52
X -5285.18 -5285.18 -5285.18 -5285.18 -5285.18 -5285.18 -5285.18 -5285.18 -5285.18 -5285.18 -5285.18 -5285.18 -5285.18 -5285.18 -5285.18 -5285.18 -5285.18 -5285.18 -5285.18 -5285.18 -5285.18
Y 757.23 680.93 604.63 528.33 452.03 375.73 299.43 223.13 146.83 70.53 -5.78 -82.08 -158.38 -234.68 -310.98 -387.28 -463.58 -539.88 -616.18 -692.48 -768.78
SOLOMON
Rev1.6 07/2002
SSD1815B 7
PIN DESCRIPTIONS
MSTAT
This pin is the static indicator driving output. It is only active in master operation. The frame signal output pin, M, should be used as the back plane signal for the static indicator. The duration of overlapping could be programmable. See Extended Command Table for details. This pin becomes high impedance if the chip is operating in slave mode.
E(RD)
This pin is MCU interface input. When interfacing to an 6800-series microprocessor, this pin will be used as the Enable (E) signal. Read/write operation is initiated when this pin is pulled high when the chip is selected. When connecting to an 8080-microprocessor, this pin receives the Read (RD) signal. Data read operation is initiated when this pin is pulled low when the chip is selected.
D 7 -D0
These pins are the 8-bit bi-directional data bus to be connected to the MCU in parallel interface mode. D7 is the MSB while D 0 is the LSB. When serial mode is selected, D7 is the serial data input (SDA) and D 6 is the serial clock input (SCK).
M
This pin is the frame signal input/output. In master mode, the pin supplies frame signal to slave devices while in slave mode, the pin receives frame signal from the master device.
CL
This pin is the display clock input/output. In master mode with internal oscillator enabled (CLS pin pulled high), this pin supplies display clock signal to slave devices. In slave mode or when internal oscillator is disabled, the pin receives display clock signal from the master device or external clock source.
VDD
Chip's Power Supply pin. This is also the reference for the DC-DC Converter output and LCD driving voltages.
VSS
Ground. A reference for the logic pins.
VSS1 DOF
This pin is display blanking control between master and slave devices. In master mode, this pin supplies on/off signal to slave devices. In slave mode, this pin receives on/off signal from the master device. Input for internal DC-DC converter. The voltage of generated, VE E, equals to the multiple factor times the potential different between this pin, VSS1, and VDD . The multiple factor, 2X, 3X or 4X, is selected by different connections of the external capacitors. All voltage levels are referenced to VDD . Note: the potential at this input pin must lower than or equal to VSS .
CS1, CS2
These pins are the chip select inputs. The chip is enabled for MCU communication only when both CS1 is pulled low and CS2 is pulled high.
VEE
This is the most negative voltage supply pin of the chip. It can be supplied externally or generated by the internal DC-DC converter, by turning on the internal voltage booster option in the Set Power Control Register command. When using internal DC-DC converter as generator, voltage at this pin is for internal reference only. It CANNOT be used for driving external circuitries.
RES
This pin is reset signal input. Initialization of the chip is started once this pin is pulled low. Minimum pulse width for completing the reset procedure is 5us.
D/C
This pin is Data/Command control pin. When the pin is pulled high, the data at D7-D0 is treated as display data. When the pin is pulled low, the data at D 7-D0 will be transferred to the command register. Details relationship with other MCU interface signals, please refer to the Timing Characteristics Diagrams.
C 3N, C 1P, C 1N , C2N and C2P
When internal DC-DC voltage converter is used, external capacitor(s) is/are connected between these pins. Different connection will result in different DC-DC converter multiple factor, 2X, 3X or 4X. Detail connections please refer to voltage converter section in the functional block description.
R/W(WR)
This pin is MCU interface input. When interfacing to an 6800-series microprocessor, this pin will be used as Read/Write (R/W) selection input. Read mode will be carried out when this pin is pulled high and write mode when low. When interfacing to an 8080-microprocessor, this pin will be the Write (WR) input. Data write operation is initiated when this pin is pulled low when the chip is selected.
VFS
This is an input pin to provide an external voltage reference for the internal voltage regulator. The function of this pin is only enabled for the External Input chip models which are required special ordering. For normal chip model, please leave this pin NC (No connection).
SSD1815B 8
Rev 1.6 07/2002
SOLOMON
VL2 , V L3, V L4 and VL5
These are the LCD driving voltage levels. All these levels are referenced to V DD. They can be supplied externally or generated by the internal bias divider, by turning on the output op-amp buffers option in the Set Power Control Register command. The potential relation of these pins are given as: VDD > VL 2 > VL3 > VL4 > VL5 > V L 6 and with bias factor, a, VL2 - VDD = 1/a * (VL6 - VDD ) VL3 - VDD = 2/a * (VL6 - VDD ) VL4 - VDD = (a-2)/a * (VL6 - V DD ) VL5 - VDD = (a-1)/a * (VL6 - V DD )
HPM
This pin is the control input of High Power Current Mode. The function of this pin is only enabled for High Power model which required special ordering. For normal models, High Power Mode is disabled and the LCD driving characteristics are the same no matter this pin is pulled High or Low. Note: This pin must be pulled to either High or Low. Leaving this pin floating is prohibited.
IRS
This is the input pin to enable the internal resistors network for the voltage regulator. When this pin is pulled high, the internal feedback resistors of the internal regulator for generating VL6 will be enabled. When it is pulled low, external resistors, R1 and R2, should be connected to VDD and VF , and VF and VL6 , respectively (see application circuit diagrams).
VL6
This pin is the most negative LCD driving voltage. It can be supplied externally or generated by turning on the internal regulator option in the Set Power Control Register command.
VF
This pin is the input of the built-in voltage regulator for generating VL6 . When external resistor network is selected (IRS pulled low) to generate the LCD driving level, V L 6, two external resistors, R 1 and R 2, should be connected between V DD and VF , and VF and VL6 , respectively (see application circuit diagrams).
ROW0 - ROW63
These pins provide the Common driving signals to the LCD panel. See Table 3 on page 10 for the COM signal mapping in SSD1815B.
SEG0 - SEG131
These pins provide the LCD segment driving signals. The output voltage level of these pins is VDD during sleep mode and standby mode.
M/S
This pin is the master/slave mode selection input. When this pin is pulled high, master mode is selected, which CL, M, MSTAT and DOF signals will be output for slave devices. When this pin is pulled low, slave mode is selected, which CL, M, DOF are required to be input from master device and MSTAT is high impedance.
ICONS
There are two ICONS pins (pin12 and 136) on the chip. Both pins output exactly the same signal. The reason for duplicating the pin is to enhance the flexibility of the LCD layout.
NC CLS
This pin is the internal clock enable pin. When this pin is pulled high, internal clock is enabled. The internal clock will be disabled when it is pulled low, an external clock source must be input to CL pin for normal operation. These are the No Connection pins. Nothing should be connected to these pins, nor they are connected together. These pins should be left open individually.
C68/80
This pin is MCU parallel interface selection input. When the pin is pulled high, 6800 series interface is selected and when the pin is pulled low, 8080 series interface is selected. If Serial Interface is selected (P/S pulled low), the setting of this pin is ignored, but must be connected to a known logic (either high or low).
P/S
This pin is serial/parallel interface selection input. When this pin is pulled high, parallel interface mode is selected. When it is pulled low, serial interface will be selected. Note1: For serial mode, D0, D1, D2, D3, D4, D5, R/W/ (WR), E/(RD) is recommended to be connected to Vss. Note2: Read Back operation is only available in parallel mode.
SOLOMON
Rev1.6 07/2002
SSD1815B 9
Table 3 ROW pin assignments for COM signals for SSD1815B .
Die Pad Name ROW0 ROW1 ROW2 ROW3 ROW4 ROW5 ROW6 ROW7 ROW8 ROW9 ROW10 ROW11 ROW12 ROW13 ROW14 ROW15 ROW16 ROW17 ROW18 ROW19 ROW20 ROW21 ROW22 ROW23 ROW24 ROW25 ROW26 ROW27 ROW28 ROW29 ROW30 ROW31 ROW32 ROW33 ROW34 ROW35 ROW36 ROW37 ROW38 ROW39 ROW40 ROW41 ROW42 ROW43 ROW44 ROW45 ROW46 ROW47 ROW48 ROW49 ROW50 ROW51 ROW52 ROW53 ROW54 ROW55 ROW56 ROW57 ROW58 ROW59 ROW60 ROW61 ROW62 ROW63 SSD1815B COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31 COM32 COM33 COM34 COM35 COM36 COM37 COM38 COM39 COM40 COM41 COM42 COM43 COM44 COM45 COM46 COM47 COM48 COM49 COM50 COM51 COM52 COM53 COM54 COM55 COM56 COM57 COM58 COM59 COM60 COM61 COM62 COM63
SSD1815B 10
Rev 1.6 07/2002
SOLOMON
FUNCTIONAL BLOCK DESCRIPTIONS
Command Decoder and Command Interface
This module determines whether the input data is interpreted as data or command. Data is directed to this module based upon the input of the D/C pin. If D/C pin is high, data is written to Graphic Display Data RAM (GDDRAM). If it low, the input at D7-D0 is interpreted as a Command and it will be decoded and be written to the corresponding command register.
MPU Parallel 8080-series interface
The parallel interface consists of 8 bi-directional data pins (D7-D0), E(RD), R/W(WR), D/C, CS1 and CS2. E(RD) input serves as data read latch signal (clock) when low provided that CS1 and CS2 are low and high respectively. Whether it is display data or status register read is controlled by D/C. R/W(WR) input serves as data write latch signal(clock) when high provided that CS1 and CS2 are low and high respectively. Whether it is display data or command register write is controlled by D/C. Refer to Figure 12 on page 28 for Parallel Interface Timing Diagram of 8080-series microprocessor. Similar to 6800-series interface, a dummy read is also required before the first actual display data read.
MPU Parallel 6800-series Interface
The parallel interface consists of 8 bi-directional data pins (D7-D0), R/W(WR), D/C, E(RD), CS1 and CS2. R/W(WR) input high indicates a read operation from the Graphic Display Data RAM (GDDRAM) or the status register. R/W(WR) input Low indicates a write operation to Display Data RAM or Internal Command Registers depending on the status of D/C input. The E(RD) input serves as data latch signal (clock) when high provided that CS1 and CS2 are low and high respectively. Refer to Figure 11 on page 27 for Parallel Interface Timing Diagram of 6800series microprocessors. In order to match the operating frequency of the GDDRAM with that of the MCU, some pipeline processing is internally performed which requires the insertion of a dummy read before the first actual display data read. This is shown in Figure 3.
MPU Serial interface
The serial interface consists of serial clock SCK (D6 ), serial data SDA (D7), D/C, CS1 and CS2. SDA is shifted into a 8-bit shift register on every rising edge of SCK in the order of D7 , D 6 ,... D0. D/C is sampled on every eighth clock to determine whether the data byte in the shift register is written to the Display Data RAM or command register at the same clock. Refer to Figure 13 on Page28 for Serial Interface Timing Diagram.
R/W(WR)
E(RD)
data bus
N write column address dummy read
n data read1
n+1 data read 2
n+2 data read 3
Figure 3 Display Data Read Back Procedure - Insertion of Dummy Read
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Oscillator Circuit
This module is an On-Chip low power RC oscillator circuitry (Figure 4). The oscillator generates the clock for the DC-DC voltage converter. This clock is also used in the Display Timing Generator.
Oscillator enable (CLS) enable Oscillation Circuit enable Buffer (CL)
Internal resistor OSC1 OSC2
Figure 4 Oscillator Circuitry
LCD Driving Voltage Generator and Regulator
This module generates the LCD voltage required for display driving output. With reference to VDD , it takes a single supply input, VSS , and generate necessary voltage levels. This block consists of:
V SS1 V EE
SSD1815B C3N C1P + C1N C2P C2N
+
C1
C1
1. 2X, 3X and 4X DC-DC voltage converter
The built-in DC-DC voltage converter is used to generate the large negative voltage supply with reference to VDD from the voltage input (VSS1). SSD1815B is possible to produce 2X, 3X or 4X boosting from the potential different between V SS1 - VDD . Detail configurations of the DC-DC converter for different boosting multiples are given in Figure 5.
V SS1 V EE
2X Boosting Configuration
SSD1815B C3N C1P + C1N C2P C2N +
2. Voltage Regulator (Voltages referenced to VDD )
The feedback gain control for LCD driving contrast curves can be selected by IRS pin to either internal (IRS pin = H) or external (IRS pin = L). If internal resistor network is enabled, eight settings can be selected through software command. If external control is selected, external resistors are required to be connected between VDD and VF (R1), and between VF and VL6 (R2). See application circuit diagrams for detail connections.
+
C1 C1 C1
3X Boosting Configuration
SSD1815B
V SS1 V EE
C3N
C1P + +
C1N
C2P C2N +
+
C1
C1
C1
C1
4X Boosting Configuration
Remarks: 1. C1 = 0.47 - 1.0uF 2. Boosting input from V SS1. 3. V SS1 should be lower potential than or equal to V SS 4. All voltages are referenced to V DD
Figure 5 DC-DC Converter Configurations
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3. Contrast Control (Voltages referenced to VDD)
Software control of the 64 contrast voltage levels at each voltage regulator feedback gain. The equation of calculating the LCD driving voltage is given as:
Contrast ) Vref VBE + R (VDD - VSS ) Vref = ( ) 1+ R VL 6 - VDD = Gain (1 +
where
Int. Reg. Resistor Ratio Setting Gain Beta
0
1
2
3
4
5
6
7
Ext. Resistor
-3.37 96.79
-3.87 96.53
-4.43 96.33
-4.99 96.06
2 (-0.15%/C) 0.52 0.43
-5.58 95.78
4 (-0.20%/C) 0.52 0.27
-6.00 95.54
-6.67 95.26
-7.27 -(1+R2/R1) 95.02 97.62
TC VBE R
0 (-0.01%/C) 0.02 0.73
7 (-0.30%/C) 0.51 0.12
*Note: There may be a calculation error of max. 6% when comparing with measurement values.
VL6 vs CONTRAST SETTINGS
-3.0000 0 10 20 30 40 50 60
-5.0000
-7.0000
IR=20H IR=21H IR=22H
VL6 [V]
IR=23H -9.0000 IR=24H IR=25H IR=26H -11.0000 IR=27H
-13.0000
-15.0000 Contrast level at VDD = 2.775V
Figure 6 Voltage Regulator Output for Different Gain/Contrast Settings
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4. Bias Divider
If the output op-amp buffer option in Set Power Control Register command is enabled, this circuit block will divide the regulator output (VL6 ) to give the LCD driving levels (V L 2 - VL5 ). A low power consumption circuit design in this bias divider saves most of the display current comparing to traditional design. Stablizing Capacitors (0.01~0.47uF) are required to be connected between these voltage level pins (VL2 - VL5 ) and VDD. If the LCD panel loading is heavy, four additional resistors are suggested to add to the application circuit as follows:
given by: * Display is turned OFF * Default Display Display Mode, 132 x 64 + 1 Icon Line * Normal segment and display data column address mapping (Seg0 mapped to Row address 00h) * Read-modify-write mode is OFF * Power control register is set to 000b * Shift register data clear in serial interface * Bias ratio is set to default, 1/9 * Static indicator is turned OFF * Display start line is set to GDDRAM column 0 * Column address counter is set to 00h * Page address is set to 0 * Normal scan direction of the COM outputs * Contrast control register is set to 20h * Test mode is turned OFF * Temperature Coefficient is set to TC0 Note: Please find more explanation in the Applications Note attached at the back of the specification.
SSD1815B
V DD V L2 V L3 V L4 V L5 V L6
R3 R4
R2
R1
Display Data Latch
+ + + + + C5 C4 C3 C2 C1
VD D Remark: 1. C1 ~ C5 = 0.01 ~ 0.47uF 2. R1 ~ R4 = 100k~ 1M
This block is a series of latches carrying the display signal information. These latches hold the data, which will be fed to the HV Buffer Cell and Level Selector to output the required voltage level. The numbers of latches are given by: 132 + 65 = 197
Figure 7 Connections for heavy loading applications
HV Buffer Cell (Level Shifter)
HV Buffer Cell work as a level shifter which translates the low voltage output signal to the required driving voltage. The output is shifted out with an internal FRM clock which comes from the Display Timing Generator. The voltage levels are given by the level selector which is synchronized with the internal M signal.
5. Bias Ratio Selection circuitry
SSD1815B can be software selected one of the bias ratios from 1/4, 1/5, 1/6, 1/7, 1/8 and 1/9. Since there will be slightly different in command pattern for different members, please refer to Command Descriptions section of this data sheet.
6. Self adjust temperature compensation circuitry
This block provides 4 different compensation settings to satisfy various liquid crystal temperature grades by software control. Default temperature coefficient (TC) setting is TC0.
Level Selector
Level Selector is a control of the display synchronization. Display voltage levels can be separated into two sets and used with different cycles. Synchronization is important since it selects the required LCD voltage level to the HV Buffer Cell, which in turn outputs the COM or SEG LCD waveform.
Graphic Display Data RAM (GDDRAM)
The GDDRAM is a bit mapped static RAM holding the bit pattern to be displayed. The size of the RAM is 132 x 65 = 8580 bits. Figure 8 on page 15 is a description of the GDDRAM address map. For mechanical flexibility, re-mapping on both Segment and Common outputs can be selected by software. For vertical scrolling of the display, an internal register storing display start line can be set to control the portion of the RAM data to be mapped to the display. Figure 8 on page 15 shows the case in which the display start line register is set to 38h. For those GDDRAM out of the display common range, they could still be accessed, for either preparation of vertical scrolling data or even for the system usage.
LCD Panel Driving Waveform
Figure 9 on page 16 is an example of how the Common and Segment drivers may be connected to a LCD panel. The waveforms provided illustrates the desired multiplex scheme.
Reset Circuit
This block includes Power On Reset circuitry and the hardware reset pin, RES. Both of these having the same reset function. Once RES receives a negative reset pulse, all internal circuitry will start to initialize. Minimum pulse width for completing the reset sequence is 5us. Status of the chip after reset is
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Common Pins SSD1815
RAM Row
RAM Column
Normal Remapped D0 (LSB) D1 D2 D3 D4 D5 D6 D7 (MSB) D0 (LSB) D1 D2 D3 D4 D5 D6 D7 (MSB) D0 (LSB) D1 D2 D3 D4 D5 D6 D7 (MSB) D0 (LSB) D1 D2 D3 D4 D5 D6 D7 (MSB) D0 (LSB) D1 D2 D3 D4 D5 D6 D7 (MSB) D0 (LSB) D1 D2 D3 D4 D5 D6 D7 (MSB) D0 (LSB) D1 D2 D3 D4 D5 D6 D7 (MSB) D0 (LSB) D1 D2 D3 D4 D5 D6 D7 (MSB) D0 (LSB) Segment Pins
00h 83h
01h 82h
02h 81h
03h 80h
****** ****** * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
80h 03h
81h 02h
82h 01h
83h 00h
Normal
Remapped
00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch 3Dh 3Eh 3Fh
Page 0
8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 0 1 2 3 4 5 6 7 ICONS 128 129 130 131
55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 63 62 61 60 59 58 57 56 ICONS
Page 1
Page 2
Page 3
Page 4
Page 5
Page 6
Page 7
Page 8
****** 0 1 2 3 ******
Figure 8 Graphic Display Data RAM (GDDRAM) Address Map with Display Start Line set to 38h.
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COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 SEG0 TIME SLOT
123456789 * . . . N+1 1 2 3 4 5 6 7 8 9 * . . . N+1 1 2 3 4 5 6 7 8 9 * . . . N+1 1 2 3 4 5 6 7 8 9 * . . . N+1
COM0
COM1
SEG0
SEG1
M
* Note : N is the number of multiplex ratio not included Icon.
Figure 9 LCD Driving Waveform for Displaying "0"
SEG1 SEG2 SEG3 SEG4 V DD V L2 V L3 V L4 V L5 V L6 V DD V L2 V L3 V L4 V L5 V L6 V DD V L2 V L3 V L4 V L5 V L6 V DD V L2 V L3 V L4 V L5 V L6
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COMMAND TABLE
Table 4 Write Command Table (D/C=0, R/W(WR)=0, E(RD)=1)
Bit Pattern 0000X 3 X 2X 1X 0 Command Set Lower Column Address Description Set the lower nibble of the column address register using X 3 X 2 X 1 X 0 as data bits. The lower nibble of column address register is reset to 0000b after POR. Set the higher nibble of the column address register using X 3X 2 X 1 X 0 as data bits. The higher nibble of column address is reset to 0000b after POR. Feedback gain of the internal regulator generating V L6 increases as X 2 X 1 X 0 increased from 000b to 111b. After POR, X 2X 1 X 0 = 100b. X 0 =0: X 0 =1: X 1 =0: X 1 =1: X 2 =0: X 2 =1: turns off the output op-amp buffer (POR) turns on the output op-amp buffer turns off the internal regulator (POR) turns on the internal regulator turns off the internal voltage booster (POR) turns on the internal voltage booster
0001X 3 X 2X 1X 0
Set Higher Column Address
00100X 2X 1X 0
Set Internal Regulator Resistor Ratio
00101X 2X 1X 0
Set Power Control Register
01X 5 X 4 X 3X 2X 1 X 0
Set Display Start Line
Set GDDRAM display start line register from 0-63 using X 5 X 4 X 3 X 2 X 1X 0. Display start line register is reset to 000000 after POR. Select contrast level from 64 contrast steps. Contrast increases (VL6 decreases) as X 5 X 4 X 3X 2X 1 X 0 is increased from 000000b to 111111b. X 5 X 4 X 3 X 2X 1X 0 = 100000b after POR X 0 =0: column address 00h is mapped to SEG0 (POR) X 0 =1: column address 83h is mapped to SEG0 Refer to Figure 8 on page 15 for example. X 0 =0: POR default bias: 1/9 X 0 =1: alternate bias: 1/7 For other bias ratio settings, see "Set 1/4 Bias Ratio" and "Set Bias Ratio" in Extended Command Set. X 0 =0: normal display (POR) X 0 =1: entire display on X 0 =0: normal display (POR) X 0 =1: reverse display X 0 =0: turns off LCD panel (POR) X 0 =1: turns on LCD panel Set GDDRAM Page Address (0-8) for read/write using X 3 X 2 X 1 X 0 X 3 =0: normal mode (POR) X 3 =1: remapped mode, COM0 to COM[N-1] becomes COM[N-1] to COM0 when Multiplex ratio is equal to N. See Figure 8 on page 15 for detail mapping. Read-Modify-Write mode will be entered in which the column address will not be increased during display data read. After POR, Read-modify-write mode is turned OFF. Initialize internal status registers. Exit Read-Modify-Write mode. RAM Column address before entering the mode will be restored. After POR, Read-modify-write mode is OFF.
10000001 * * X5 X 4 X 3 X 2 X 1X 0
Set Contrast Control Register
1010000X 0
Set Segment Re-map
1010001X 0
Set LCD Bias
1010010X 0
Set Entire Display On/Off
1010011X 0
Set Normal/Reverse Display
1010111X 0
Set Display On/Off
1011X 3 X 2X 1X 0 1100X 3 * * *
Set Page Address Set COM Output Scan Direction
11100000
Set Read-Modify-Write Mode
11100010 11101110
Software Reset Set End of Read-Modify-Write Mode
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Table 4 Write Command Table (D/C=0, R/W(WR)=0, E(RD)=1)
1010110X 0 Set Indicator On/Off X 0 = 0: indicator off (POR, second command byte is not required) X 0 = 1: indicator on (second command byte required) X1 X0 X1 X0 X1 X0 X1 X0 = = = = 00: 01: 10: 11: indicator off indicator on and blinking at ~1 second interval indicator on and blinking at ~1/2 second interval indicator on constantly
* * * * * * X 1 X0
Indicator Display Mode, This second byte command is required ONLY when "Set Indicator On" command is sent. NOP Test Mode Reset Set Test Mode Set Power Save Mode (Standby or Sleep)
11100011 11110000 1111 * * * * ********
Command result in No Operation Reserved for IC testing. Do NOT use. Reserved for IC testing. Do NOT use. Standby or sleep mode will be entered using compound commands. Issue compound commands "Set Display Off" followed by "Set Entire Display On".
Table 5 Extended Command Table
Bit Pattern 10101000 00X 5 X 4 X 3X 2X 1 X 0 Command Set Multiplex Ratio Description To select multiplex ratio N from 2 to the maximum multiplex ratio (POR value) for each member (including icon line). Max. mux ratio: 65 N = X 5 X 4 X 3X 2X 1 X 0 + 2, eg. N = 001111b + 2 = 17 X1 X0 = 00 1/8 or 1/6 000: 010: 100: 111: 001, 01 1/6 or 1/5 10 1/9 or 1/7 (POR) 11 Prohibited
10101001 X 7 X 6 X 5 X 4X 3X 2 X 1 X 0
Set Bias Ratio (X 1 X 0 )
Set TC Value (X 4 X 3 X 2)
X4 X3 X2 = X4 X3 X2 = X4 X3 X2 = X4 X3 X2 = X4 X3 X2 =
-0.01%/C (TC0, POR) -0.15%/C (TC2) -0.20%/C (TC4) -0.30%/C (TC7) 011, 101, 110: Reserved
Modify Osc. Freq. (X 7X 6X 5 )
Increase the value of X7 X 6 X 5 will increase the oscillator frequency and vice versa. Default Mode: X 7 X 6 X 5 = 011 (POR for SSD1815B) : Typ. 19kHz High Frequency Mode: X 7 X 6 X 5 = 110 (For SSD1815B) : Typ. 23kHz X 0 = 0: use normal setting (POR) X 0 = 1: fixed at 1/4 bias The On/Off of the Static Icon is given by 3 phases/1 phase overlapping of the M and MSTAT signals. This command set total phases of the M/MSTAT signals for each frame. The more the total phases, the less the overlapping time and thus the lower the effective driving voltage. X 5 X 4 = 00: 3 phases X 5 X 4 = 01: 5 phases X 5 X 4 = 10: 7 phases (POR) X 5 X 4 = 11: 16 phases After POR, X 5X 4 X 3 X 2 X 1 X 0 = 0 After setting mux ratio less than default value, data will be displayed at Center of matrix. To move display towards Row 0 by L, X 5 X 4 X 3 X 2 X 1X 0 = L To move display away from Row 0 by L, X 5 X 4 X 3 X 2X 1 X 0 = 64-L Note: max. value of L = (POR default mux ratio - display mux)/2
1010101X 0
Set 1/4 Bias Ratio
11010100 00X 5 X 4 0000
Set Total Frame Phases
11010011 00X 5 X 4 X 3X 2X 1 X 0
Set Display Offset
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Table 6 Read Command Table (D/C=0, R/W(WR)=1, E=1(RD=0))
Bit Pattern D 7D 6 D 5D 4 D3 D 2 D1 D 0 Command Status Register Read Description D 7=0: indicates the driver is ready for command. D 7=1: indicates the driver is Busy. D 6=0: indicates reverse segment mapping with column address. D 6=1: indicates normal segment mapping with column address. D 5=0: indicates the display is ON. D 5=1: indicates the display is OFF. D 4=0: initialization is completed. D 4=1: initialization process is in progress after RES or software reset. D 3D 2 D 1D 0 = 0010, these 4-bit is fixed to 0010 which could be used to identify as Solomon Systech Device.
Note:
Patterns other than that given in Command Table and Extended Command Table are prohibited to enter to the chip as a command. Otherwise, unexpected result will occurs.
Data Read / Write
To read data from the GDDRAM, input High to R/W(WR) pin and D/C pin for 6800-series parallel mode, Low to E(RD) pin and High to D/C pin for 8080-series parallel mode. No data read is provided in serial interface mode. In normal data read mode, GDDRAM column address pointer will be increased by one automatically after each data read. However, no automatic increase will be performed in read-modify-write mode. Also, a dummy read is required before first valid data is read. See Figure 3 on page 11 in Functional Block Descriptions section for detail waveform diagram. To write data to the GDDRAM, input Low to R/W(WR) pin and High to D/C pin for both 6800-series and 8080-series parallel mode. For serial interface mode, it is always in write mode. GDDRAM column address pointer will be increased by one automatically after each data write. It should be noted that, after the automatic column address increment, the pointer will NOT wrap round to 0 when overflow (>131). The incrementation of the pointer stops at 131. Therefore there is a need to re-initialize the pointer when progress to another page address. Table 7 Automatic Address Increment
D/C 0 0 1 R/W(WR) 0 1 0 Action Write Command Read Status Write Data Auto Address Increment No No Yes
1 1 Read Data Yes*1 *1. If read data is issued in read-modify-write mode, address will not be increased automatically.
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COMMAND DESCRIPTIONS
Set Lower Column Address
This command specifies the lower nibble of the 8-bit column address of the display data RAM. The column address will be increased by each data access after it is pre-set by the MCU.
Set LCD Bias
This command is used to select a suitable bias ratio required for driving the particular LCD panel in use. The selectable values of this command are 1/9 or 1/7. For other bias ratio settings, extended commands should be used.
Set Entire Display On/Off Set Higher Column Address
This command specifies the higher nibble of the 8-bit column address of the display data RAM. The column address will be increased by each data access after it is pre-set by the MCU. This command forces the entire display, including the icon row, to be illuminated regardless of the contents of the GDDRAM. In addition, this command has higher priority than the normal/reverse display. This command is used together with "Set Display Display ON/OFF" command to form a compound command for entering power save mode. See "Set Power Save Mode" later in this section.
Set Internal Regulator Resistors Ratio
This command is to enable any one of the eight internal resistor sets for different regulator gain when using internal regulator resistor network (IRS pin pulled high). In other words, this command is used to select which contrast curve from the eight possible selections. Please refer to Functional Block Descriptions section for detail calculation of the LCD driving voltage.
Set Normal/Reverse Display
This command turns the display to be either normal or reversed. In normal display, a RAM data of 1 indicates an illumination on the corresponding pixel, while in reversed display, a RAM data of 0 will turn on the pixel. It should be noted that the icon line will not affect, that is not be reversed, by this command.
Set Power Control Register
This command turns on/off the various power circuits associated with the chip. There are three power relating sub-circuits could be turned on/off by this command. Internal voltage booster is used to generated the large negative voltage supply (V E E) from the voltage input (V SS1 - VDD ). An external negative power supply is required if this option is turned off. Internal regulator is used to generate the LCD driving voltage. V L 6, from the negative power supply, VEE . Output op-amp buffer is the internal divider for dividing the different voltage levels (VL 2, VL3 , VL4 , VL5 ) from the internal regulator output, VL6 . External voltage sources should be fed into this driver if this circuit is turned off.
Set Display On/Off
This command is used to turn the display on or off. When display off is issued with entire display is on, power save mode will be entered. See "Set Power Save Mode" later in this section for details.
Set Page Address
This command enters the page address from 0 to 8 to the RAM pager register for read/write operations. Please refer to Figure 8 on page 15 for detail mapping.
Set Display Start Line
This command is to set Display Start Line register to determine starting address of display RAM to be displayed by selecting a value from 0 to 63. With value equals to 0, D0 of Page 0 is mapped to COM0. With value equals to 1, D1 of Page0 is mapped to COM0 and so on. Display start line values of 0 to 63 are assigned to Page 0 to 7. Please refer to Figure 8 on page 15 as an example for display start line set to 56 (38h).
Set COM Output Scan Direction
This command sets the scan direction of the COM output allowing layout flexibility in LCD module assembly. See Figure 8 on page 15 for the relationship between turning on or off of this feature. In addition, the display will have immediate effect once this command is issued. That is, if this command is sent during normal display, the graphic display will have vertical flipping effect.
Set Contrast Control Register
This command adjusts the contrast of the LCD panel by changing the LCD drive voltage, VL 6, provided by the On-Chip power circuits. V L 6 is set with 64 steps (6-bit) in the contrast control register by a compound commands. See Figure 10 for the contrast control flow.
Set Contrast Control Register Contrast Level Data
No
Set Segment Re-map
This command changes the mapping between the display data column addresses and segment drivers. It allows flexibility in mechanical layout of LCD glass design. Please refer to Figure 8 on page 15 for example.
Changes Complete? Yes
Figure 10 Contrast Control Flow
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Set Read-Modify-Write Mode
This command puts the chip in read-modify-write mode in which: 1. column address is saved before entering the mode 2. column address is increased only after display data write but not after display data read. This Ready-Modify-Write mode is used to save the MCU's loading when a very portion of display area is being updated frequently. As reading the data will not change the column address, it could be get back from the chip and do some operation in the MCU. Then the updated data could be write back to the GDDRAM with automatic address increment. After updating the area, "Set End of Read-Modify-Write Mode" is sent to restore the column address and ready for next update sequence.
Set Power Save Mode
Entering Standby or Sleep Mode should be done by using a compound command composed of "Set Display ON/OFF" and "Set Entire Display ON/OFF" commands. When "Set Entire Display ON" is issued when display is OFF, either Standby Mode or Sleep Mode will be entered. The status of the Static Indicator will determine which power save mode is entered. If static indicator is off, the Sleep Mode will be entered: * Internal oscillator and LCD power supply circuits are stopped * Segment and Common drivers output VDD level * The display data and operation mode before sleep are held * Internal display RAM can still be accessed If the static indicator is on, the chip enters Standby Mode which is similar to sleep mode except addition with: * Internal oscillator is on * Static drive system is on Please also be noted that during Standby Mode, if the software reset command is issued, Sleep Mode will be entered. Both power save modes can be exited by the issue of a new software command or by pulling Low at hardware pin RES .
Software Reset
Issuing this command causes some of the chip's internal status registers to be initialized: * Read-Modify-Write mode is exited * Static indicator is turned OFF * Display start line register is cleared to 0 * Column address counter is cleared to 0 * Page address is cleared to 0 * Normal scan direction of the COM outputs * Internal regulator resistors Ratio is set to 4 * Contrast control register is set to 20h
Status register Read
This command is issued by pulling D/C Low during a data read (refer to Figure 11 on page 27 and Figure 12 on page 28 for parallel interface waveforms). It allows the MCU to monitor the internal status of the chip. No status read is provided for serial mode.
Set End of Read-Modify-Write Mode
This command relieves the chip from read-modify-write mode. The column address before entering read-modify-write mode will be restored no matter how much modification during the read-modify-write mode.
EXTENDED COMMANDS
These commands are used, in addition to basic commands, to trigger the enhanced features designed for the chip.
Set Indicator On/Off
This command turns on or off the static indicator driven by the M and MSTAT pins. When the "Set Indicator On" command is sent, the second command byte "Indicator Display Mode" must be followed. However, the "Set Indicator Off" command is a single byte command and no second byte command is required. The status of static indicator also controls whether standby mode or sleep mode will be entered, after issuing the power save compound command. See "Set Power Save Mode" later in this section.
Set Multiplex Ratio
This command switches default multiplex ratio to any multiplex mode from 2 to the maximum multiplex ratio (POR value), including the icon line. Max. mux ratio: 65 The chip pins ROW0-ROW63 will be switched to corresponding COM signal output, see Table 8 on page 21 for examples of 18 multiplex (including icon line) settings without and with 7 lines display offset for SSD1815B. It should be noted that after changing the display multiplex ratio, the bias ratio may also need to be adjusted to make display contrast consistent.
NOP
A command causing the chip takes No OPeration.
Set Test Mode
This command force the driver chip into its test mode for internal testing of the chip. Under normal operation, users should NOT apply this command.
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Rev1.6 07/2002
SSD1815B 21
Table 8 Row pin assignments for COM signals in 18 mux display (including icon line) with/without 7 line display offset towards ROW0.
SSD1815B Die Pad Name ROW0 ROW1 ROW2 ROW3 ROW4 ROW5 ROW6 ROW7 ROW8 ROW9 ROW10 ROW11 ROW12 ROW13 ROW14 ROW15 ROW16 ROW17 ROW18 ROW19 ROW20 ROW21 ROW22 ROW23 ROW24 ROW25 ROW26 ROW27 ROW28 ROW29 ROW30 ROW31 ROW32 ROW33 ROW34 ROW35 ROW36 ROW37 ROW38 ROW39 ROW40 ROW41 ROW42 ROW43 ROW44 ROW45 ROW46 ROW47 ROW48 ROW49 ROW50 ROW51 ROW52 ROW53 ROW54 ROW55 ROW56 ROW57 ROW58 ROW59 ROW60 ROW61 ROW62 ROW63 No Offset X X X X X X X X X X X X X X X X X X X X X X X COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 X X X X X X X X X X X X X X X X X X X X X X X X 7 lines Offset X X X X X X X X X X X X X X X X COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
Note: X - Row pin will output non-selected COM signal.
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SOLOMON
Set Bias Ratio
Except the 1/4 bias, all other available bias ratios could be selected using this command plus the "Set LCD Bias" command. For detail setting values and POR default, please refer to the extended command table, Table 5 on page 18.
Set Temperature Coefficient (TC) Value
4 different temperature coefficient settings is selected by this command in order to match various liquid crystal temperature grades. Please refer to the extended command table, Table 5 on page 18, for detail TC values.
Modify Oscillator Frequency
The oscillator frequency can be fine tuned by applying this command. Since the oscillator frequency will be affected by some other factors, this command is not recommended for general usage. Please contact SOLOMON Systech Limited application engineers for more detail explanation on this command.
Set 1/4 Bias Ratio
This command sets the bias ratio directly to 1/4. This bias ratio is especially designed for use in under 12 mux display. In order to restore to other bias ratio, this command must be executed, with LSB=0, before the "Set Multiplex ratio" or "Set LCD Bias" command is sent.
Set Total Frame Phases
The total number of phases for one display frame is set by this command. The Static Icon is generated by the overlapping of the M and MSTAT signals. These two pins output either VS S or VDD at same frequency but with phase different. To turn on the Static Icon, 3 phases overlapping is applied to these signals, while 1 phase overlapping is given to the Off status. The more the total number of phases in one frame, the less the overlapping time and thus the lower the effective driving voltage at the Static Icon on the LCD panel.
Set Display Offset
This command should be sent ONLY when the multiplex ratio is set less than SSD1815B's default value. When a lesser multiplex ratio is set, the display will be mapped in the middle (y-direction) of the LCD, see the no offset columns on Table 8 on page 21. Use this command could move the display vertically within the 64 commons. To make the Reduced-Mux Com 0 (Com 0 after reducing the multiplex ratio) towards the Row 0 direction for L lines, the 6bit data in second command should be given by L. An example for 7 line moving towards to Com0 direction is given on Table 8 on page 21. To move in the other direction by L lines, the 6-bit data should be given by 64-L. Please note that the display confined within SSD1815B's default multiplex value. That is the maximum value of L is given by the half of the default value minus the reduced-multiplex ratio. For an odd display mux after reduction, moving away from Row 0 direction will has 1 more step.
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Rev1.6 07/2002
SSD1815B 23
MAXIMUM RATINGS
Table 9 Maximum Ratings* (Voltage Reference to VSS )
Symbol V DD V EE V in Input Voltage Supply Voltage Parameter Value -0.3 to +4.0 0 to -12.0 V SS -0.3 to V DD+0.3 25 -30 to +85 -65 to +150 Unit V V V This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions to be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation it is recommended that Vin a n d Vout be constrained to the range VSS < or = (V in or V out ) < or = V DD. Reliability of operation is enhanced if unused input are connected to an appropriate logic voltage level (e.g., either VSS o r VDD ). Unused outputs must be left open. This device may be light sensitive. Caution should be taken to avoid exposure of this device to any light source during normal operation. This device is not radiation protected.
I TA T stg
Current Drain Per Pin Excluding V DD and V SS Operating Temperature Storage Temperature Range
mA C C
* Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the limits in the Electrical Characteristics tables or Pin Description section.
DC CHARACTERISTICS
Table 10 DC Characteristics (Unless otherwise specified, Voltage Referenced to VSS , VDD = 2.4 to 3.5V, T A = -30 to 85C.)
Symbol V DD Parameter Logic Circuit Supply Voltage Range Test Condition Recommend Operating Voltage Possible Operating Voltage V DD = 2.7V, Voltage Generator On, 4X DC-DC Converter Enabled, Write accessing, T cyc =3.3MHz, Typ. Osc. Freq., Display On, no panel attached. V DD = 2.7V, V EE = -8.1V, Voltage Generator Disabled, R/W (WR) Halt, Typ. Osc. Freq., Display On, V L6 - V DD = -9V, no panel attached. V DD = 2.7V, V EE = -8.1V, Voltage Generator On, 4x DC-DC Converter Enabled, R/ W(WR) Halt, Typ. Osc. Freq., Display On, V L6 - VDD = -9V, no panel attached. V DD = 2.7V, LCD Driving Waveform Off, Typ. Osc. Freq., R/W(WR) halt. V DD = 2.7V, LCD Driving Waveform Off, Oscillator Off, R/W(WR) halt. Display On, Voltage Generator Enabled, DC-DC Converter Enabled, Typ. Osc. Freq., Regulator Enabled, Divider Enabled. Voltage Generator Disabled. Min 2.4 1.8 Typ 2.7 300 Max 3.5 3.5 600 Unit V V A
IAC
Access Mode Supply Current Drain (V D D Pins)
IDP1
Display Mode Supply Current Drain (V D D Pins)
-
60
100
A
IDP2
Display Mode Supply Current Drain (V D D Pins)
-
150
200
A
A 3.5 10 A 0.2 5
ISB
Standby Mode Supply Current Drain (V D D Pins) Sleep Mode Supply Current Drain (V DD Pins) LCD Driving Voltage Generator Output (V EE Pin)
ISLEEP
V EE
-12.0
-
-1.8
V
V LCD
LCD Driving Voltage Input (V EE Pin)
-12.0
-
-1.8
V
SSD1815B 24
Rev 1.6 07/2002
SOLOMON
Table 10 DC Characteristics (Unless otherwise specified, Voltage Referenced to VSS , VDD = 2.4 to 3.5V, T A = -30 to 85C.)
Symbol V OH1 V OL1 V L6 Parameter Logic High Output Voltage Logic Low Output Voltage LCD Driving Voltage Source (V L6 Pin) Iout=-100 A Iout=100A Regulator Enabled (V L6 voltage depends on Int/Ext Contrast Control) Regulator Disable Test Condition Min 0.9*VDD 0 V EE-0.5 Typ Max V DD 0.1*VDD V DD Unit V V V
V L6 V IH1 V IL1 V L2 V L3 V L4 V L5 V L6 V L2 V L3 V L4 V L5 V L6 IOH IOL IO Z
LCD Driving Voltage Source (V L6 Pin) Logic High Input voltage Logic Low Input voltage LCD Display Voltage Output (V L2, VL3 , VL4, VL5 , VL6 Pins)
0.8*VDD 0
Floating 1/a*V L6 2/a*V L6 (a-2)/a*V L6 (a-1)/a*V L6 V L6 -
V DD 0.2*VDD V DD V L2 V L3 V L4 V L5 -50 1
V V V V V V V V V V V V V A A A A pF %
Voltage reference to V DD, Bias Divider Enabled, 1:a bias ratio
V L3 V L4 V L5 V L6 -12V 50 -1
LCD Display Voltage Input (V L2, VL3 ,VL4, VL5 , VL6 Pins)
Voltage reference to V DD, External Voltage Generator, Bias Divider Disabled
Logic High Output Current Source Logic Low Output Current Drain Logic Output Tri-state Current Drain Source Logic Input Current Logic Pins Input Capacitance Variation of VL6 Output (V DD is fixed)
V out = VDD -0.4V V out = 0.4V
IIL/II H CIN V L6
-1 Regulator Enabled, Internal Contrast Control Enabled, Set Contrast Control Register = 0 -3
5 0
1 7.5 3
TC0 TC2 TC4 TC7
Temperature Coefficient Compensation Flat Temperature Coefficient (POR) Temperature Coefficient 2* Temperature Coefficient 4* Temperature Coefficient 7*
Voltage Voltage Voltage Voltage
Regulator Regulator Regulator Regulator
Enabled Enabled Enabled Enabled
0 -0.12 -0.17 -0.25
-0.01 -0.15 -0.20 -0.30
-0.12 -0.17 -0.25 -
% /C % /C % /C % /C
* The formula for the temperature coefficient is: V ref at 50C - Vref at 0C X 50C - 0C 1 V ref at 25C X 100%
TC(%) =
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Rev1.6 07/2002
SSD1815B 25
AC CHARACTERISTICS
Table 11 AC Characteristics (Unless otherwise specified, Voltage Referenced to VSS , VDD = 2.4 to 3.5V, T A = 25C.)
Symbol FOSC Parameter Oscillation Frequency of Display Timing Generator for: * SSD1815B Test Condition Internal Oscillator Enabled (default), VDD = 2.7V 17 Remark: Oscillation Frequency vs Temperature change (-20C to 70C): -0.5%/ C * FFRM Frame Frequency for: * SSD1815B 19 21 kHz Min Typ Max Unit
132 x 64 Graphic Display Mode, Display ON, Internal Oscillator Enabled 132 x 64 Graphic Display Mode, Display ON, Internal Oscillator Disabled, External clock with freq., F ext, feeding to CL pin.
FOSC 4 x 65
Hz
* The formula for Oscillation Frequency vs Temperature Change:
%change (F osc) = F osc at 70C - Fosc at -20C 70C - (-20C) X 1 F osc at 25C X 100%
Frame Frequency vs. Temperature
95 90 Frame frequency [Hz] 85 80 75 70 65 60 55 50 -40 -20 0 20 40
o
Frame Frequency vs. Temperature
60
80
100
Temperature [ C]
Test Condition : VDD = 2.775V, TA = 25C, default contrast and internal resistor gain are used.
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Rev 1.6 07/2002
SOLOMON
Table 12 6800-Series MPU Parallel Interface Timing Characteristics (VDD - VSS = 2.4 to 3.5V, TA = -30 to 85C)
Symbol tcycle tAS tAH tDSW tDHW tDHR tOH tACC PW CSL Clock Cycle Time Address Setup Time Address Hold Time Write Data Setup Time Write Data Hold Time Read Data Hold Time Output Disable Time Access Time Chip Select Low Pulse Width (read) Chip Select Low Pulse Width (write) Chip Select High Pulse Width (read) Chip Select High Pulse Width (write) Rise Time Fall Time Parameter Min 300 0 0 40 15 20 120 60 60 60 Typ Max 70 140 15 15 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns
PW CSH
tR tF
R/W
D/C
tAS E tcycle PW CSL CS1 (CS2=1) tF tDSW D0 -D7 (Write data to driver) Valid Data tR
tAH
P WCSH
tDHW
tACC D 0 -D 7 (Read data from driver) Valid Data
tDHR
tO H
Figure 11 6800-series MPU Parallel Interface Characteristics
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Rev1.6 07/2002
SSD1815B 27
Table 13 8080-Series MPU Parallel Interface Timing Characteristics (VDD - VSS = 2.4 to 3.5V, TA = -30 to 85C)
Symbol tcycle tAS tAH tDSW tDHW tDHR tOH tACC PW CSL Clock Cycle Time Address Setup Time Address Hold Time Write Data Setup Time Write Data Hold Time Read Data Hold Time Output Disable Time Access Time Chip Select Low Pulse Width (read) Chip Select Low Pulse Width (write) Chip Select High Pulse Width (read) Chip Select High Pulse Width (write) Rise Time Fall Time Parameter Min 300 0 0 40 15 20 120 60 60 60 Typ Max 70 140 15 15 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns
PW CSH
tR tF
D/C
tAS
tAH
CS1 (CS2=1) tcycle PW CSL PWCSH RD
WR tF tDSW D 0 -D 7 (Write data to driver) Valid Data tR tDHW
tACC D 0-D 7 (Read data from driver) Valid Data
tDHR
tOH
Figure 12 8080-series MPU Parallel Interface Characteristics
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Rev 1.6 07/2002
SOLOMON
Table 14 Serial Interface Timing Characteristics (V DD - VSS = 2.4 to 3.5V, T A = -30 to 85C)
Symbol tcycle tAS tAH tCSS tCSH tDSW tDHW tCLKL tCLKH tR tF Clock Cycle Time Address Setup Time Address Hold Time Chip Select Setup Time (for D 7 input) Chip Select Hold Time (for D 0 input) Write Data Setup Time Write Data Hold Time Clock Low Time Clock High Time Rise Time Fall Time Parameter Min 250 150 150 120 60 100 100 100 100 Typ Max 15 15 Unit ns ns ns ns ns ns ns ns ns ns ns
D/C tAS CS1 (CS2=1) tCSS tcycle tCLKL SCK tF tDSW SDA Valid Data tR tDHW tCLKH tAH tCSH
D/C CS1 (CS2=1) SDA D7 D6 D5 D4 D3 D2 D1 D0
SCK
Figure 13 Serial Interface Characteristics
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Rev1.6 07/2002
SSD1815B 29
APPLICATION EXAMPLES
ICONS COM0 : COM10 COM11 : COM30 COM31
DISPLAY PANEL SIZE 132 x 64 + 2 X ICON LINES
COM32 COM33 : : : COM63 ICONS
SEG0 --------------------------------------------- SEG131
Segment Remapped [Command: A1] COM32 COM33 COM34 : : : : : : : : COM51 COM52 SEG131 --------------------------------------------------------------------------------------------------------------------------------SEG0 ICONS COM0 : COM4 COM5 COM6 COM7 : : : COM18 COM19
Remapped COM SCAN Direction [Command: C8]
SSD1815B IC
64 MUX ( DIE FACE UP)
CO M20 : CO M26 CO M27 : CO M31 ICO NS CO M63 : CO M57 CO M56 : CO 53 M
Remapped COM SCAN Direction [Command: C8]
VDD VL2 VL3 VL4 VL5 VL6
[Command: C8] SCAN Direction Remapped COM
VF
Remapped COM SCAN Direction [Command: C8]
R2 VSS[GND] D/C D0 - D7 RES /CS1 R/W VEE IRS
0.1~0.47uF x 5
R1 Optional for External Resistors Gain Control [IRS must be pulled to GND]
VDD=2.75V
External Vneg=-9.5V
Logic pin connections not specified above: Pins connected to V DD : CS2, RD , M/S, CLS, C68/80, P/S, HPM Pins connected to V S S: VSS1 Figure 14 Application Circuit of 132 x 64 plus 2 icon lines using SSD1815B, configured with: external VEE , internal regulator, divider mode enabled (Command: 2B), 6800-series MPU parallel interface, internal oscillator and master mode.
SSD1815B 30
Rev 1.6 07/2002
SOLOMON
ICONS COM0 : COM10 COM11 : COM30 COM31
DISPLAY PANEL SIZE 132 x 64 + 2 X ICON LINES
COM32 COM33 : : : COM63 ICONS
SEG0 --------------------------------------------- SEG131
Segment Remapped [Command: A1] COM32 COM33 COM34 : : : : : : : : COM51 COM52 SEG131 --------------------------------------------------------------------------------------------------------------------------------SEG0 ICONS COM0 : COM4 COM5 COM6 COM7 : : : COM18 COM19
Remapped COM SCAN Direction [Command: C8]
SSD1815B IC
64 MUX ( DIE FACE UP)
CO M20 : CO M25 CO M26 : CO M31 ICO NS CO M63 : CO M59 CO M58 : CO 53 M
Remapped COM SCAN Direction [Command: C8]
VSS VEE C3N C1P C1N C2N C2P
VDD VL2 VL3 VL4 VL5 VL6
[Command: C8] SCAN Direction Remapped COM
VF
Remapped COM SCAN Direction [Command: C8]
R2 D0 - D7 and Control Bus RES
0.47~1uF x 4
VSS [GND]
0.1~0.47uF x 5
R1
VDD=2.75V
Optional for External Resistors Gain Control [IRS must be pulled to GND]
Logic pin connections not specified above: Pins connected to V DD : CS2, RD , M/S, CLS, C68/80, P/S, HPM Pins connected to V S S: VSS1 Pins floating: DOF, CL, VFS Figure 15 Application Circuit of 132 x 64 plus 2 icon lines using SSD1815B, configured with all internal power control circuit enabled, 6800-series MPU parallel interface, internal oscillator and master mode.
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Rev1.6 07/2002
SSD1815B 31
APPENDIX A - TAB INFORMATION
Figure 16 SSD1815BT TAB Drawing 1/2
SSD1815B 32
Rev 1.6 07/2002
SOLOMON
Copper View Pin Assignment
Figure 17 SSD1815BT TAB Drawing 2/2
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Rev1.6 07/2002
SSD1815B 33
Figure 18 SSD1815BT2 TAB Drawing 1/2
SSD1815B 34
Rev 1.6 07/2002
SOLOMON
Internal Connections: VDD : CS2, M/S VSS : VSS1
Figure 19 SSD1815BT2 TAB Drawing 2/2
SOLOMON
Rev1.6 07/2002
SSD1815B 35
APPENDIX B - TAB WHEEL INFORMATION
A
3.5mm
CORE DIA. 25.8mm KEYWAY = 4.2mm
W2 A MATERIAL: HIGH IMPACT POLYSTYRENE (HIPS) SURFACE RESISTIVITY: 1 X 10 5 OHM MIN 1 X 109 OHM MAX TAPE LENGTH = 20m SECTION AA
35mm TAB W2 370.2 mm
48mm TAB 500.2 mm
70mm TAB 700.2 mm
Figure 20 TAB Wheel Mechanical Drawing
330mm
SSD1815B 36
Rev 1.6 07/2002
SOLOMON
Solomon Systech reserves the right to make changes without further notice to any products herein. Solomon Systech makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Solomon Systech assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application b customer's technical experts. y Solomon Systech does not convey any license under its patent rights nor the rights of others. Solomon Systech products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Solomon Systech product could create a situation where personal injury or death may occur. Should Buyer purchase or use Solomon Systech products for any such unintended or unauthorized application, Buyer shall indemnify and hold Solomon Systech and its offices, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, d irectly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Solomon Systech was negligent regarding the design or manufacture of the part.
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